HIGH-EFFICIENT VLSI ARCHITECTURE FOR THREE OPERAND BINARY ADDER

This paper presents a VLSI architecture for three-operand binary adder. The proposed design is based on carry-select adder (CSLA) and Han-Carlson (HCA) Carry-select known its high speed low power consumption. uses novel carry-in selection scheme that reduces the number of logic gates required carry generation. Additionally, (HCA), parallel prefix two-operand adder, can also be used addition, significantly reducing critical path delay at cost supplementary hardware. In addition to perform with less space consumption, high-speed area-efficient suggested. pre-compute bitwise followed by carry-selection computation logic. includes processing unit allows efficient multiple operands results simultaneously. has been implemented in Verilog HDL synthesized using 32nm CMOS technology. simulation show achieves performance easily scaled handle larger without sacrificing or area overhead. When compared current approaches, suggested lowest ADP PDP.